Our Unique Plating Technology

Electrolytic UBM Plating: Wafer Bumps & Lines

Plating micro bumps and fine wiring is essential for miniaturization and enhanced functionality in semiconductor packaging. With over 20 years of experience in semiconductor wafer plating technology, we contribute to solving customer challenges and realizing products. We support small-scale prototypes and testing projects, starting from a single piece, and are also available for mass production inquiries.

Key Functions: Bondability high conductivity low resistance wiring formation

Main Substrates

Supported Substrates

Sizes: 4, 6, 8, 12 (please contact us for other sizes)
Materials: Si, SiC, GaAs, InP, glass, sapphire, ceramics, other compound semiconductors

Track Record

Prototyping

Electrolytic Copper (Cu)	Wiring, rewiring (RDL), hybrid bonding, Cu sintering bonding, low resistance, heat dissipation
Electrolytic Nickel (Ni)	Barrier metal (diffusion prevention)
Electrolytic Gold (Au)	Solder bonding, wire bonding, Au-Au bonding, ACF bonding, oxidation resistance, low resistance
Electrolytic Tin-Silver (SnAg) Alloy	Lead-free bonding
Electrolytic Gold-Tin (AuSn) Alloy	High-temperature bonding
Electrolytic Rhodium (Rh)	Surface hardness, wear resistance
Electrolytic Indium (In)	Low-temperature bonding

* Please feel free to contact us about specifications not listed above.

Features

Bump, Wiring, and Pad Plating Lineup

We offer tailored bump, wiring, and pad plating technologies to meet your product design, application, and challenge needs. Contact us for more details.

Plating Types: Cu, Ni, Au, SnAg, AuSn, In, Rh, and more
Combinations available: Cu/Ni/Au, Cu/Ni/SnAg, Ni/Au, Cu/SnAg, and others.
Inquire about other plating types.
Plating Thickness: Thin to thick films, up to approximately 100 μm, based on your requirements.
Substrate Sizes: From Φ4 to 12 inches
Contact us for other sizes, thin wafers (around 100 μm), square shapes, or special materials/shapes.
Plating Options: Supports both patterned and full-area bump and wiring plating.
More Information: Refer to downloadable materials for detailed specifications.

Φ20μm x height 30μm Ni/SnAg bump plating — Φ20μm x height 30μm Ni/SnAg plating

Φ25μm x height 55μm Cu/Ni/Au bump plating — Φ20μm x height 30μm Ni/SnAg plating

Plating and Integrated Processes with Seed Formation and Photolithography

In addition to plating for bump and wiring formation, we provide a full range of processes, including seed layer formation through sputtering, resist patterning via exposure/development, and the removal of resist and seed layers. Our advanced equipment and technology allow us to deliver these processes as a complete solution, helping reduce your design timeline.

Sputtering: We create thin film seed layers of Ti, Cu, Al, and Ni.
Note: Film thickness and layer composition can be customized to your requirements.
Photolithography: Our aligner-type exposure equipment supports everything from mask creation.
Electroplating: Please refer to the previous section.
Resist Stripping: We can strip resist materials based on their composition.
Seed Stripping: We etch Ti and Cu seed layers formed by sputtering.

*Note: Our selective etching minimizes side-etching.

Diagram showing the process steps from sputtering to resist layer stripping in electroplating.

Microbumps / Fine-Line Plating Solutions

Our integrated process allows for the formation of microbumps and fine-line wiring.

Minimum bump size: Φ10μm x H10μm
Minimum wiring line: L/S = 10μm/10μm x H15μm

For plating-only processes, we have experience in even finer and smaller patterns.

Minimum bump size: Below Φ5μm
Minimum wiring line: L/S = 3/3μm or smaller

*Please consult with us as the capabilities may vary depending on plating thickness and shape.

*For detailed specifications, please refer to the downloadable materials.

Φ10 μm x height 13 μm Ni/Au bump plating

L/S = 10/10 μm, copper wiring plating with a height of 15 μm. — Φ10 μm x height 13 μm Ni/Au bump plating

Wiring Plating for Substrates with Height Variations

Even for substrates with height variations, which are necessary for 3D and high-density mounting, we offer wiring plating that conforms to the substrate’s contours.

・Wiring width can be reduced to as small as 30μm
・Wiring formation is possible even for steep slopes up to 300μm in depth

*Note: Please consult with us as the response may vary depending on the slope and shape of the substrate.

High-precision wiring plating on a substrate following height variations, with 30 μm width wires.

Plating wire technology that adapts to high-low substrate differences with 300 μm depth and 30 μm width. — High-precision wiring plating on a substrate following height variations, with 30 μm width wires.

Downloadable Materials

Wafer Size & Process Compatibility Chart
Bump Diameter & Height Compatibility Chart
Bump Plating Process Examples
Wiring Plating Process Examples

Request Free Resources here

FAQs

Can you handle not only round shapes like wafers but also split or chip shapes?

Depending on the shape, we may be able to accommodate your request. Please contact us for more details.
Can you process plating types or specifications not listed above?

We may be able to accommodate your request depending on the specifics. Please contact us for more details. Please note that additional time may be required for preparation.
Is it possible to handle substrates with thin thicknesses?

It depends on the material, but we have experience working with thicknesses around 100μm.
Can you perform partial processes like sputtering only, photolithography only, or stripping only, in addition to plating?

Yes, we can accommodate those requests. However, some specific requirements may not be possible, so please contact us for further details.
How is the exposure mask for photolithography created?

We will arrange the creation of the mask based on the drawing data you provide. Please provide the drawing in either DXF or DWG format.

Applications and Use Cases

Used in MEMS-based ASIC devices
Used in sensor devices
Used in other devices